Step By Step VHDL Programming for Xilinx FPGA & CPLD Project
Genre: eLearning | MP4 | Video: h264, 1280x720 | Audio: aac, 48000 Hz
Language: English | VTT | Size: 5.78 GB | Duration: 10 section | 79 lectures | (8h 38m)

What you'll learn
VHDL Programming Synthesis & Simulation Xilinx FPGA & CPLD Devices Xilinx ISE Design Suite Implementation & Program Downloading
Requirements
Digitial Logic Design Concepts Basic knowledge of any Programming Language ( Like Ex. C Programming )
Description
Description : Contents of this PCB Design Course are developed using a VHDL language for Xilinx ISE Design Suite , Design Software , for Xilinx based FPGAs & CPLDs devices . This Tool supports to Windows & Linux Platforms . The VHDL Programs runs on all Editions of Xilinx ISE Design Suite , including Xilinx ISE Webpack Edition , which is a Free Download Edition after completing successful Registration procedure with Xilinx ( On Xilinx Website ) .

Course Learning Duration - You can Learn VHDL Programming within a Day , provided you have prior knowledge of Digital Electronics Fundamentals & any Programming language like C Programming .

This Course is mainly designed for Beginners / Engineering Students / Hobbyists .

Video Content is explained with Short Video sessions in a simple way for better understanding , even for the Beginners .

In this course you will learn about -

Digital Logic Design Concepts

Digital Logic Families

VHDL Language Basics - VHDL Syntax , Literals , Data Types .

VHDL Structure - Entity , Architecture , Library, Package .

VHDL Process .

VHDL - Sequential & Concurrent Statements .

Target Device Selection for Programming ( FPGA or CPLD )

VHDL Programming ( Design / Source Code )

VHDL Test bench ( Source Code )

Simulation Using ISim

Synthesis ( With RTL & Technology Schematic )

Constraints ( Pin Locking )

Implementation

Programming ( Downloading )

VHDL Programming Examples :

- Logic Gates

- MUX (Multiplexers )

- Decoder

- Encoder

- Half Adder & Full Adder

- D Latch

- D Flip Flop

- FSM - Finite state Machine using VHDL

- Counter

- Shift Register

- ALU - Arithmetic & Logic Unit

- Memory Unit - RAM

- Memory Unit - ROM

- VHDL Project : BUS Controller

Instructor has more than a 22 Years of Design / Training Experience after M.Tech. in Electronics Design & Technology , which includes the Experience in Electronic Circuit Design , Embedded System / VLSI , VHDL & Verilog Programming for Xilinx FPGAs , CPLDs using Xilinx ISE Suite & Xilinx Vivado Tool , PSOC1 using Cypress PSOC Designer & PSOC3 using Cypress PSOC Creator , Microcontroller Programming for MCS-51 (8051 ) family using Keil uVision 4 , Programming ATMega 16/32/128 using Atmel AVR Studio , Programming Microchip PIC 16/18 using MPLAB , Arduino Programming for Arduino Uno , Raspberry Pi & Raspbian Linux , Python Programming with Python 3.8 ( IDLE) , Python Thonny , Python Pycharm , Anaconda Navigator - Jupyter Notebook , Spyder Python , Google Colab , Crouzet Millenium 3 for PLC Programming & also PCB design which includes PCB Softwares such as EasyEDA , Eagle , KiCad 5.1 , Fritzing & Express PCB .

Who this course is for:
Beginners , Hobbyists , Teachers & anyone who is interested to Learn to Create Digital Logic Designs , using FPGA / CPLD . University Students , Students from Engineering colleges & Polytechnic Institutes , who want to create the Design for their Programmable Electronics based Academic Project . Anyone who wants to make career in FPGA , VHDL Programming . Electronic Designers / Embedded Engineers / Electronic Circuit Design Professionals , who are new to VHDL Programming & FPGA / CPLD Device Architectures .


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