MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz, 2 Ch
Genre: eLearning | Language: English + .srt | Duration: 5 lectures (47m) | Size: 248.6 MB

SystemVerilog is the most adopted language to design and verify complex integrated circuits.

Get started with SystemVerilog

SystemVerilog interface, basic & advanced modelling concepts

SystemVerilog interface, modport, clocking

Verilog, Digital Design

Good hands-on Verilog design skills

IEEE 1800 LRM defines the standard in great detail. One of the key features of SystemVerilog is interfaces - a key element that is common to both RTL designers and verification eeers. In this course, you will learn the motivation to use interfaces, get deep into the syntax and semantics of the construct. The course also includes a set of industry examples to show how this is used in real life.

VLSI enthusiasts, Verilog designers, RTL Designers, Verification Eeers, Managers



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