Xilinx Vivado Design Suite HLx Editions 2018.2 + LogiCORE IP | 17.41 GB
Development environment for FPGA, CPLD firm Xilinx. During the installation phase of the Vivado Design Suite HLx Editions, the program will ask for the installation option:
Vivado HL WebPACK, Vivado HL Design Edition or Vivado HL System Edition.
Extras. The information: In the new release of Vivado 2018.2 HLx Editions the support of following families of microcircuits is added:
• Zynq UltraScale + RFSoC: XCZU21DR (-1, -2, -2LE), XCZU25DR (-1, -2, -2LE), XCZU27DR (-1, -2, -2LE), XCZU28DR (-1, -2, - 2LE), XCZU29DR (-1, -2, -2LE);
• XA Zynq UltraScale + MPSoC: XAZU4EV (-1, -1L, -1Q), XAZU5EV (-1, -1L, -1Q);
• Defense-Grade Zynq UltraScale + MPSoCs: XQZU5EG (-1M), XQZU5EV (-1M);
• Spartan-7: XC7S6 (-1, -2, -1L), XC7S15 (-1, -2, -1L);
• Artix-7: XC7A12T (-3), XC7A25T (-3).
Year / Release Date: 2018
Release: 2018.2
Developer: Xilinx Inc.
Bit depth: 64bit
Language: English
Tabletka: present
System requirements: OS: Linux (64 bit) / Windows 7, 10 (64 bit)
Minimum Disk Space: 20 GB
Recommended Physical RAM: 3 GB - 32 GB (depends on the family of chips)
What News?
Partial reconfiguration support for Zynq-7000 devices with a single-core processor (Z-7007S, Z-7012S, Z-7014S)
New color detection example and new liner algebra block(QR inverse) in Model Composer
New Schedule Viewer in Vivado HLS to graphically display dependencies of operations and control steps
Zynq UltraScale+ RFSoC production devices support in System Generator
Production devices introduced in this release
Zynq UltraScale+ RFSoC: XCZU21DR (-1,-2,-2LE), XCZU25DR (-1,-2,-2LE), XCZU27DR (-1,-2,-2LE), XCZU28DR (-1,-2,-2LE), XCZU29DR (-1,-2,-2LE)
Zynq UltraScale+ MPSoC: XAZU4EV (-1,-1L,-1Q), XAZU5EV (-1,-1L,-1Q), XQZU5EG (-1M), XQZU5EV (-1M)
Artix®-7 and Spartan®-7: XC7S6 (-1,-2,-1L), XC7S15 (-1,-2,-1L), XC7A25T (-3), XC7A12T (-3)
New devices enabled in WebPACK
XA Zynq Ultrascale+ MPSoC: XAZU4EV, XAZU5EV
Spartan-7: XC7S6, XC7S15
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